The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, to a semiconductor device equipped with a magnetic resistor and a manufacturing method of the device.
As one mode of semiconductor devices, there is an MRAM (magnetic random access memory) using a magnetoresistive element called MTJ (magnetic tunnel junction). In the MRAM, magnetoresistive elements are placed at positions where digit lines extending in one direction intersect with bit lines extending in a direction substantially perpendicular thereto and they are formed in an array form. Magnetoresistive elements each has two magnetic layers stacked one after another while having therebetween a tunnel insulating film.
In recent years, for reducing power consumption, the MRAM has adopted an interconnect structure including a cladding layer as a structure of digit lines and bit lines which causes a magnetic field to selectively act on the magnetoresistive element. The cladding layer has a function of shielding a magnetic field. In the digit line located below the magnetoresistive element, therefore, the cladding layer covers the side surfaces and the bottom surface of the digit line except the upper surface of the digit line located immediately below the magnetoresistive element. In the bit lines located above the magnetoresistive element, on the other hand, the cladding layer covers the side surfaces and the upper surface of the bit line except the bottom surface of the bit line immediately above the magnetoresistive element. There have conventionally been proposed various kinds of MRAMs using such a cladding layer.
For example, a magnetic memory device described in Japanese Patent Laid-Open No. 2004-40006 is equipped with a first interconnect, a second interconnect sterically intersecting with the first interconnect, and a tunnel magnetoresistive element which is electrically insulated from the first interconnect but is electrically coupled to the second interconnect and has, in a cross region of the first interconnect and the second interconnect, a tunnel insulating layer sandwiched between ferromagnetic bodies.
This magnetic memory device has a contact portion for coupling the tunnel magnetoresistive element to an interconnect layer and this contact portion couples an interconnect layer provided below the first interconnect to the tunnel magnetoresistive element and is formed in a coupling hole penetrating through the first interconnect.
The magnetic memory device has further a flux concentrator comprised of a high magnetic permeability film on both side surfaces of the first interconnect and on the surface of the first interconnect opposite to the surface facing to the tunnel magnetoresistive element.
Japanese Patent Laid-Open No. 2003-318365 describes a magnetic random access memory equipped with a TMR element and a write word line located immediately below the TMR element. The write word line is covered, at both side surfaces and the bottom surface thereof, with a yoke material having a high magnetic permeability.
International Patent Publication No. 2002-58166 describes a magnetic storage device having a magnetoresistive element, a conductor for generating a flux for causing a change in resistance of the magnetoresistive element, and a magnetic yoke having this conductor placed inside thereof.
Japanese Patent Laid-Open No. 2005-340715 describes a magnetic memory device having a memory portion comprised of a TMR element obtained by stacking a magnetization fixed layer, a tunnel barrier layer, and a magnetization free layer one after another. A write word line is placed opposite to the TMR element via an insulating layer. A high magnetic permeability layer is provided so that it reaches the side surface side of the TMR element from the bottom of the write word line.
Japanese Patent Laid-Open No. 2004-31640 describes a magnetic memory device equipped with a MOS transistor formed on a silicon substrate, an interlayer insulating film formed on the silicon substrate, and a plurality of TMR elements buried in the interlayer insulating film.
This magnetic memory device has a write bit line and a write word line placed so as to sandwich each TMR element therebetween and a yoke portion formed on the surfaces of the write bit line and the write word line except the surface facing the TMR element.
Japanese Patent Laid-Open No. 2006-310423 describes a magnetic memory equipped with a memory cell having a magnetoresistive element, a write interconnect through which a write current for generating a write magnetic field flows upon writing information to the memory cell, and a ferromagnetic film covering therewith at least a portion of the surfaces of the write interconnect except the surface facing the memory cell.
[Patent Documents]
    [Patent Document 1] Japanese Patent Laid-Open No. 2004-40006    [Patent Document 2] Japanese Patent Laid-Open No. 2003-318365    [Patent Document 3] International Patent Publication No. 2002-58166    [Patent Document 4] Japanese Patent Laid-Open No. 2005-340715    [Patent Document 5] Japanese Patent Laid-Open No. 2004-31640    [Patent Document 6] Japanese Patent Laid-Open No. 2006-310423